1. Field of the Invention
Embodiments of the invention relate to the field of semiconductor, and more specifically, to device packaging.
2. Description of Related Art
As semiconductor technology advances for higher processor performance, the frequency of logic and memory devices increases for higher speed. The balance between speed performance and power consumption becomes a challenging design problem. In the power delivery loop, both for core and input/output (I/O) power, parasitic inductance and resistance associated with the die package and/or printed circuit board cause a drop in voltage available to the device, leading to performance decrease.
Existing techniques to reduce voltage drop in power delivery loop have a number of disadvantages. De-coupling capacitors are added to the package to store charges and deliver to the device when required. However, de-coupling capacitors on a chip-scale package (CSP) increases the package form factor which is undesirable for many applications such as cellular phones. The height of high value capacitors may be higher than the total height of a multi-die stacked CSP and therefore such capacitors may be not used. Inductors are used in the voltage regulator for power delivery and/or phase-locked loop (PLL), band gap filter, or other radio frequency (RF) components to increase power performance. Resistors are used to dampen the resonance which is generated from the package inductance and on-chip capacitance. Placing these components at the package increase package form factor and interconnect parasitic losses.